The novelty of APRICOT lays in application of the HLDD design representation model advantages for simulation-based and formal verification tasks (e.g. assertion checking and code coverage analysis).
APRICOT is an acronym for Assertions checking (monitoring), formal PRoperty checkIng, verification COverage measurement and Test pattern generation. Behind the name stands a hardware verification framework developed by Tallinn University of Technology.
The novelty of APRICOT lies in the usage of the High-Level Decision Diagrams (HLDD) design representation model advantages for the mentioned above verification tasks.
APRICOT verification framework
The framework is aimed at both education and research. The APRICOT verification framework is easy to use because of the variety of the available interfaces to the common design formats such as VHDL, SystemC, PSL and EDIF.
As it follows from its name decryption, the framework supports a wide range of verification tasks that alternatively would require a set of different commercial CAD tools. All the tools of APRICOT are based on an efficient single design representation model and allow homogeneous verification flow (See figure above). Recently published experimental results show the advantages of HLDD-based verification tools compared to the tools from the major CAD vendors.
